Advanced semiconductor devices with high performance are required to have multi-level layers, fine patterns to obtain high speed transmission. CMP process is indespensable to have well-planarized interlayer dielectric or metals in LSI and accomplish the above requirments.
Features
Free form scratches by using tuned CeO2 particles.
High removal rate at low slurry content (CeO2:1%).
High planarization and selectivity between SiO2 and Si3N4.